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MEMS Ambisonic Microphone (Underway)

Overview

This project pushes the boundaries of spatial audio capture by combining a digital MEMS microphone array with high-performance signal processing on FPGA and Teensy platforms.

Architectural Key Points

1. Processing Core: Tang Nano 9K FPGA

At the heart of the system, a Tang Nano 9K (Gowin GW1NR-9) manages the high-speed bitstream from the MEMS array.

  • Synchronous Acquisition: Guarantees zero-sample phase drift between all capsules (A-Format), critical for spatial accuracy.
  • DSP Pipeline: Real-time CIC decimation and FIR compensation filters implemented in Verilog.
  • Interfacing: Ultra-low latency data transfer to the Teensy 4.1 via a custom high-speed synchronous bus.

2. Interface & Communication (Teensy 4.1)

The Teensy 4.1 receives the processed data and manages the USB communication stack.

  • ASIO Support: Integration of a custom ASIO driver for minimal latency within DAWs (Digital Audio Workstations).
  • Format Conversion: Real-time conversion from A-Format to B-Format (WXYZ).

Results

To follow